1. Field
This invention pertains to the field of memory systems, and more particularly, to the field of memory systems employing error correction decoding.
2. Description
In some flash memory systems, a multi-channel error correction coder (ECC) architecture is employed with buffer memories for encoding/decoding the data from the host system to and from the flash memory.
FIG. 1 shows a block diagram of such a flash memory system 10. Flash memory system 10 includes a flash memory controller 100 and a memory block 200. Memory controller 100 includes a host interface 110, a user data buffer 120, a system data buffer 130, a NAND interface 140, and a central processing unit 150, all connected together by a system bus 160. NAND interface 140 includes a direct memory access (DMA) controller 144 and an error correction coder (ECC) block 145. ECC block 145 includes a plurality (N) of ECC modules, including ECC modules 141, 142 and 143. Memory block 200 includes a plurality (N) of NAND memory devices, including memory devices 211, 212 and 213. Connected between each of the ECC modules 141, 142 and 143 and a corresponding one of the memory devices 211, 212 and 213 is a channel 0, 1, N, etc.
FIG. 2 illustrates in greater detail interconnections between ECC block 145 and memory devices 211, 212 and 213 in flash memory system 10. As seen in FIG. 2, ECC module 141 includes encoder 161, and decoder block 165, which further comprises detector 162 and corrector 163. Likewise, ECC module 142: includes encoder 171, and decoder block 175, which further comprises detector 172 and corrector 173; and ECC module 143 includes encoder 181, and decoder block 185, which further comprises detector 182 and corrector 183.
In operation, data from a host device (e.g., a processor) destined to be stored in a memory device 211, for example, is sent by DMA controller 144 to ECC module 141. In ECC module 141, the data is first encoded by the encoder 161 and then transmitted to memory device 211 via channel 0. When data is to be read from memory device 211 and provided to a host device, it is first decoded by decoder 165 and then the decoded data is supplied to DMA controller 144. In decoder 165, detector 162 detects whether any errors are present in the data received from memory device 211, and if there are any errors, then corrector 163 corrects the errors.
FIG. 3 illustrates conventional decoding operations of one exemplary embodiment of a decoder block, such as decoder block 165 in ECC 141 in FIG. 2, such as decoder block 165 in ECC 141 in FIG. 2 for error correction decoding of data received from a memory device. In the example of FIG. 3, the error correction decoder is a Bose-Chaudhuri-Hocquenghem (BCH) decoder. In particular, FIG. 3 illustrates the timing of decoding operation for each sector of data read from a memory device (e.g., memory device 211). In a first period T0-T1, upon receiving data for an Nth sector from memory device 211, in a step 310 a syndrome computer in the decoder computes the syndrome to determine whether any errors are present in the received data. If the syndrome values are zero, then it is determined that the received data has no errors.
Otherwise, in a second period T1-T2, in a step 320 a key equation solver (KES) block solves the key equation and in a step 330 a Chien search and error evaluator (CSEE) block determines the error values and error locations. Finally, in a third period T2-T3, in a step 350 an error corrector (e.g., corrector 163) in ECC 141 corrects the errors using error values from an error locator/evaluator buffer 370 as the data is read out of decoder block 165. Then ECC 141 is ready to repeat the above-described process for the next (N+1)th sector of data. In the example illustrated in FIG. 3, the first period T0-T1 has 526 clock cycles, the second period T1-T2 has 372 clock cycles, and the third period T2-T3 has 300 clock cycles.
In a memory system having memory devices with low bit-density cells, the error rate in the device will be relatively low, and so the error detection and correction is not critical in view of the total system performance. However, in a memory system with memory devices using a high bit-density single-bit/cell structure, or having a multi-bit/cell structure, then the errors that occur in reading data from the memory devices are greater, requiring more detection and correction steps, and this reduces the read performance in the memory system.
Accordingly, it would be desirable to provide a memory system that can provide robust error detection and correction with an improved throughput. It would also be desirable to provide a memory system that can sustain a high read performance when using memory devices using a high bit-density single-bit/cell structure, or having a multi-bit/cell structure.
The present invention is directed to a memory system, and a method of processing data in a memory system.
In one aspect of the inventive concept, a memory system comprises a memory controller including an error correction decoder. The error correction decoder comprises: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively, an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.
In another aspect of the inventive concept, a method is provided in a memory system for processing data received by a memory controller from a memory device. The method comprises: receiving data from a memory device; demultiplexing the received data into a first set of data and a second set of data; storing the first set of data into a first buffer memory; determining whether the first set of data includes any errors, while storing the second set of data into a second buffer memory; multiplexing the first set of data from the first buffer memory and the second set of data from the second memory buffer; providing the multiplexed data to an error corrector; and correcting one or more errors in the first set of data with the error corrector while determining whether the second set of data includes any errors.